FIELD OF THE INVENTION
The invention lies in the field of semiconductor manufacture. More specifically, the invention relates to a method for improving the identifiability or readability of alignment marks on semiconductor wafers during multilayer metallization, in which the alignment marks are fabricated in the scribe line and vias or contact holes or plated-through holes to deeper metallization layers or active regions by means of a photolithographic patterning step in an oxide layer by etching and subsequent deposition of metal, and in which the semiconductor wafer is subsequently planarized in a CMP step (polishing step), with subsequent aluminum (Al) metallization.
Alignment marks are indispensable for the photolithographic processing of semiconductor wafers. Alignment marks help ensure that the masks which are necessary for exposing the photoresist on the semiconductor wafer can be aligned exactly with respect to the latter. This presupposes that the alignment marks have an exact assignment to the structures to be fabricated on the semiconductor wafer and, furthermore, offer a sufficient topographical contrast to be able to be reliably identified. After each CMP process, in particular, the identification of these alignment marks is greatly impaired due to the topographical contrast which is severely reduced or absent on account of the polishing operation. The consequence is an increased outlay on postprocessing on account of the misalignment of the mask. It may even happen that alignment becomes completely impossible. This problem is becoming ever greater, however, on account of the ever decreasing structure widths and the consequentially increasing requirements made of the alignment accuracy.
In order, if possible, to circumvent or at least reduce these problems, two alternatively usable methods have been employed in the prior art.
In one of those processes, the alignment marks are located at such a depth that a topography which offers a sufficient contrast still remains after the CMP process. See FIG. 1. It is disadvantageous in that case, however, that the inner edges of the alignment marks can be displaced or flattened in an uncontrolled manner due to unavoidable asymmetric erosion of the oxide surrounding the alignment mark. An overlay error is consequently produced during wafer exposure. Such an error necessitates post processing of the semiconductor wafer. In this case, this overlay error on account of displacement of the detected edge position can occur either at the alignment marks within a wafer, or from wafer to wafer or from batch to batch.
A further disadvantage of particularly deep alignment marks may be seen in the fact that considerable quantities of particles and slurry residues may remain in the alignment marks, particularly after the CMP process, and involve the risk of contamination and an increased defect density. Since these particles can also settle on the edges of the alignment mark, this results in further flattening of the edges. The consequence is that exact alignment is at the very least made more difficult, if not even impossible. Consequently, the readability of the alignment marks cannot be improved sufficiently by that method.
In the second prior art method, an additional photoplane is used. See FIG. 2. Using the additional photoplane, a further alignment mark (auxiliary mark) is etched in the scribe line before metallization and is intended to allow better alignment after metallization due to sharper edges. This is made possible by virtue of the fact that the additional alignment mark can be aligned more easily relative to the tungsten-filled marker, owing to the fact that the material contrast between the additional alignment mark and the surrounding oxide can be utilized. The outlay for the additional photoplane and the fact that the overlay error of the two markers accumulates are disadvantageous in this case.